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The XCore XS1 is a 32-bit RISC microprocessor architecture designed by XMOS. The architecture is designed to be used in multi-core processors for embedded systems. Each XS1 core executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling. The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an event (e.g. a message, time, or external I/O event) before continuing. Processors with this architecture include the XCore XS1-G4 and XCore XS1-L1. ==Architecture== The architecture comprises a central execution unit that operates on a set of 25 registers, and surrounded by a number of ''resources'' that perform operations that interact with the environment. Each thread has its own set of hardware registers, enabling threads to execute concurrently. The instruction set comprises both a (more or less standard) sequential programming model, and instructions that implement multi-threading, multi-core and I/O operations. Most instructions can access only the 12 general-purpose registers r0–r11. In general, they are completely interchangeable, except that some instructions use r11 implicitly. There are also 4 base registers usable by some instructions: * r12 = cp = Constant pool pointer * r13 = dp = Data pointer * r14 = sp = Stack pointer * r15 = lr = Link register Registers 16 through 24 are only accessible to specialized instructions. Except for the first two (r16 = pc = program counter, r17 = sr = status register), they are dedicated to exception and interrupt handling. The status register contains various mode bits, but the processor does ''not'' have the standard ALU result flags like carry, zero, negative or overflow. Add and subtract with carry instructions exist, but specify 5 operand registers: 2 inputs and input carry, and one output and output carry. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「XCore XS1」の詳細全文を読む スポンサード リンク
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